Feb 13, 2014 #1 A andy2000akimo Member level 1 Joined Sep 17, 2009 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,491 in standard cmos process . how to working in na current ? I ever try use mos current mirror when bias cureent less < 0.1ua some die have fail yield loss .. even simulation by hspice is ok , but real silicion have fail die how to design total 20na LDO ?? bandgap need current , OPA also need operation current
in standard cmos process . how to working in na current ? I ever try use mos current mirror when bias cureent less < 0.1ua some die have fail yield loss .. even simulation by hspice is ok , but real silicion have fail die how to design total 20na LDO ?? bandgap need current , OPA also need operation current
Feb 13, 2014 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 Perhaps it's not exactly standard CMOS? Could you show the data sheet?
Feb 17, 2014 #3 A andy2000akimo Member level 1 Joined Sep 17, 2009 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,491 MCP1710 , not MPC MCP1710 Data Sheet - Microchip ww1.microchip.com/downloads/en/.../25158A.pdf翻譯這個網頁 provides high-current and low-output voltages, while maintaining an ultra-low 20 nA of quiescent current during device operation. In addition, the MCP1710 can.
MCP1710 , not MPC MCP1710 Data Sheet - Microchip ww1.microchip.com/downloads/en/.../25158A.pdf翻譯這個網頁 provides high-current and low-output voltages, while maintaining an ultra-low 20 nA of quiescent current during device operation. In addition, the MCP1710 can.