Jan 29, 2009 #1 R rajsrikanth Full Member level 2 Joined Apr 19, 2006 Messages 130 Helped 12 Reputation 24 Reaction score 4 Trophy points 1,298 Location Hyderabad Activity points 1,947 about delays in verilog hi everyone i want to know how the delay is taken in verilog like if we give #40 what does it mean. is it mean 40ns/s delay or 40 clock pulses delay. can any one help me on this isssue. regards srikanth
about delays in verilog hi everyone i want to know how the delay is taken in verilog like if we give #40 what does it mean. is it mean 40ns/s delay or 40 clock pulses delay. can any one help me on this isssue. regards srikanth
Jan 29, 2009 #2 D dinesh.4126 Member level 5 Joined Feb 27, 2008 Messages 83 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,841 Re: about delays in verilog Assign delay using assign #10 y=a&b basically used in Test Bench.In design its not syntesizable .
Re: about delays in verilog Assign delay using assign #10 y=a&b basically used in Test Bench.In design its not syntesizable .