about delays in verilog #40 is 40 ns/s or 40 clock pulses?

[rajsrikanth]

about delays in verilog

hi everyone

i want to know how the delay is taken in verilog
like if we give
#40 what does it mean. is it mean 40ns/s delay or 40 clock pulses delay.
can any one help me on this isssue.


regards
srikanth

 

[dinesh.4126]

Re: about delays in verilog

Assign delay using assign #10 y=a&b basically used in Test Bench.In design its not syntesizable .