If there is an CMOS opamp, whose input differencial pair is matched well, and also the internal circuits are well matched. Then how much will the offset voltage be for the real fab-out device? Is 10mV the normal level? And is it dependent much on the process capability?
Thanks.
If there is an CMOS opamp, whose input differencial pair is matched well, and also the internal circuits are well matched. Then how much will the offset voltage be for the real fab-out device? Is 10mV the normal level? And is it dependent much on the process capability?
Thanks.
hi, as i know, the offset of vth is 10mv or so in common conditions. i concerned if reduce the vgs-vth and make input pair saturate easy, but Delt(vth)/(vgs-vth) seems more sensitive and bring new 'offset'
it's my self option, i wonder the truth..Hah
In most processes Avt is 4-5mV/um. Is better for PMOS and worse for NMOS (PMOS has better matching).
E.g. two transistors with areas of 1 sq um will have an offset with sigma of 4-5mV, wich is 98-99% of the chips will be withing 12-15mV (3*sigma). If designed right of course.
This law does not scale with technology, and toghther with flicker noise and lower headroom is one of the largest obstacle in scaling down the analog design.