shrbht
Full Member level 1
design flow 0.13
I'm a beginer in ASIC design . can anyone tell me about ASIC design flow for 0.13um logic. what tools used?
I know little from RTL to gdsII
synthesis --- synopsys DC
prelayout STA ----- PrimeTime
P&R -----Astro or SOC encounter
verification ---- calibre or hecules or Assure
postlayout STA ----PrimeTime
how about DFT? in synthesis ? what tool? DFT compiler?
how about Power analysis or SI ?
I'm a beginer in ASIC design . can anyone tell me about ASIC design flow for 0.13um logic. what tools used?
I know little from RTL to gdsII
synthesis --- synopsys DC
prelayout STA ----- PrimeTime
P&R -----Astro or SOC encounter
verification ---- calibre or hecules or Assure
postlayout STA ----PrimeTime
how about DFT? in synthesis ? what tool? DFT compiler?
how about Power analysis or SI ?