module counter (clk, reset, hour, min, sec);
input clk, reset;
output reg [7:0] hour, min, sec;
always @ (posedge clk or posedge reset) begin
if (reset==1) begin
hour[3:0] <= 0;
hour[7:4] <= 0;
min[3:0] <= 0;
min[7:4] <= 0;
sec[3:0] <= 0;
sec[7:4] <= 0;
end else if (sec[3:0] < 4'b1001) begin
sec[3:0] <= sec[3:0] + 1;
end else begin
sec[3:0] <= 0;
if (sec[7:4] < 4'b0101) begin
sec[7:4] <= sec[7:4] + 1;
end else begin
sec[7:4] <= 0;
if (min[3:0] < 4'b1001) begin
min[3:0] <= min[3:0] + 1;
end else begin
min[3:0] <= 0;
if (min[7:4] < 4'b0101) begin
min[7:4] <= min[7:4] + 1;
end else begin
min[7:4] <= 0;
if (hour[7:4] < 4'b0010) begin
if (hour[3:0] < 4'b1001) begin
hour[3:0] <= hour[3:0] + 1;
end else begin
hour[3:0] <= 0;
hour[7:4] <= hour[7:4] + 1;
end
end else begin
if (hour[3:0] < 4'b0011) begin
hour[3:0] <= hour[3:0] + 1;
end else begin
hour[7:4] <= 0;
hour[3:0] <= 0;
end
end
end
end
end
end
end
endmodule