tia_design
Advanced Member level 4
2 stage cmos op amp
I'm using 0.35 um CMOS process and designed a typical 2-stage folded-cascode opamp with PMOS diff pair. The second stage is common source one. Vth for NMOS is 0.6V and PMOS is -0.74V. Bias current for input pare is 3uA for M1 and M0 each with size150/1, while output stage bias current is about 11uA and PMOS size is 38.4/0.7 and NMOS size is 19.2/0.7. The first stage gain is 55dB, and second stage gain is 33dB. My concern is that:
1. Why second stage gain is so big. Normally it is about 20-30dB, right?
2. the length of output MOSFET M16 and M17 is 0.7uM, short channel still show up, right? If I choose length as 1uM for M16 and M17, the second stage gain will be 38dB and total op amp gain will be >90dB for those mosfet model.
Thanks for any comments about my question and my design
I'm using 0.35 um CMOS process and designed a typical 2-stage folded-cascode opamp with PMOS diff pair. The second stage is common source one. Vth for NMOS is 0.6V and PMOS is -0.74V. Bias current for input pare is 3uA for M1 and M0 each with size150/1, while output stage bias current is about 11uA and PMOS size is 38.4/0.7 and NMOS size is 19.2/0.7. The first stage gain is 55dB, and second stage gain is 33dB. My concern is that:
1. Why second stage gain is so big. Normally it is about 20-30dB, right?
2. the length of output MOSFET M16 and M17 is 0.7uM, short channel still show up, right? If I choose length as 1uM for M16 and M17, the second stage gain will be 38dB and total op amp gain will be >90dB for those mosfet model.
Thanks for any comments about my question and my design