A TSPC DFF sizing & simulation

[hugo92]

Hi , As a project i'm triyng to simulate a TSPC Flip flop that works correct.
I don't know where s the problem that my program works incorrect.
This is the Pos edge TSPC flip flop:

This is sizing I choosed:

And this is my Hspice simulation waves:
it's obvious that flip flop isn't working fine.

This is a correct flip flop waves working fine which somebody else sent me:

can u please help me .

I think my hspice code is ok , anyway its here:

FO1,FO2,FO3,FO4 are 4 inverters as capacitive load in the output node(Q).
and also I used a buffer before input signals in order to have real signals.

 

[Dominik Przyborowski]

1) .param lmin=16nm - I am pretty sure m is not recognizable here
2) net gnd is floating. Use gnd! or 0 instead.

 

[hugo92]

1) .param lmin=16nm - I am pretty sure m is not recognizable here
2) net gnd is floating. Use gnd! or 0 instead.

Hi , thanks it deleted two warnings but didn't improve simulation result

 

[hugo92]

The problem solved with assigning Wn > Wp in all 3 branches & m6 , m7 = m4 , m5