A strange phenominon about current mirror

[chang830]

hi,
Pls. take a look at the attached diagram of a current mirror.

This is a 1:100 current mirror. The NMOS CAP is added here to keep the gate from rippling. In designing/simulation, it is OK. The current ratio is good for all the PVT corners.

But the silicon test is disillusionary. The ratio of current mirror have large excursion from the design value. It is about only 1:80, when the input current is samll, the ratio of current mirror is even low to 1:60.

Another interesting thing is that the ratio of the current mirror have a positive linearly temperature coeffcients.I.e, when the temperature increases, the ratio increased also. While in simulatiion, it is independed with the temperature.

Would anyone help to find any issues with my circuit?

BTW, the process is 0.5um CMOS processs.
Thanks in advance

 

[pixel]

Set for mosfets at the one side L=0.6u+ Δ, where Δ is for example 0.05u. Then simulate.

 

[gevy]

What are nodes voltages in this circuit ? V_IN and V_OUT ?

 

[laoud]

Of course they are not V_IN and V_OUT nodes.These are the input and output nodes of the current mirror,so these are currents.The problem is very strange!!!

 

[zxcynosure]

I think for current mirror, channel length should be longer to reduce CLM effect. Also, for large conversion ratio, large current side has lower Rdson, if it can not be large enough to satisfy the ideal current source assumption (with infinite rds), it will have impact.

 

[deepa]

Well the mismatch could be beacuse of the bias dependency of Vt's of the transistors .

 

[hr_rezaee]

Hi
the answer is mismatch.
in practice, it is better to choose the ratio of current mirror less than 10.
don't forget mont carlo analysis!!!
regards

 

[hung_wai_ming@hotmail.com]

Hi you have two questions here. Let me answer the first one. Second one looks a bit weird.

Your device size 20/0.6um is definitely not a good choice for current mirror.
I really don't understand how you can match your layout with such weird m factor
and also the cascoded m=3 factor. Definitely your device has been TOTALLY mismatched. If you did some decap and SEM for the transistors, you will know why your current mirror has changed. It is VERY easy in your case the diode connected transistors have been edged in process to a smaller gate length since it has few transistors surrounding them, while the legs are edged in a relatively larger length. As a result, it is highly possible that 20/0.6 -> 20/0.58 for diode connected transistor and 20/0.6 -> 20/0.61 for leg transistors (m=100). As a result, your current ratio got to be MUCH LESS than simulation. If you don't believe, try do de-cap and SEM to measure the results and let us know.

The second question looks a bit odd where the current increases with temperature. May i know where the connection of bulk? VDD or source ?

Anyway, I bet you didn't understand correctly what should be the analog design?
I really think how come you can have the gut to tape out with such device sizes?
If you take look to any analog book, no authors won't suggest you use odd number as the current mirror and such large multiples as the leg current. Also, looks like no one would suggest you add such a BIG capacitor with resistor as the ripple reduction. IT's TOTALLY not practical

Added after 4 minutes:

What is the margin of VDS to VDS(sat) in simulation?
if you transistor behaves like a resistor due to not enough margin, it's highly possible you got current increases with temperature

Anyway, as an advice, pls think TWICE before your next tape out as the failure of tape out will cause one to have no confidence next time and finally just think analog design is difficult, while the the truth. "Analog design success is reserved to those with full preparation"

 

[jiesteve]

Hung,

Don't understand why the m=3 cascode factor is so bad? Why is that? Ignore the 1:100 factor of the original poster for a moment...

 

[MSSN]

Are u sure that the linear temperature coefficient is of the mirroring ratio and that it isn't the temperature coefficient of the input current.

 

[chang830]

Are u sure that the linear temperature coefficient is of the mirroring ratio and that it isn't the temperature coefficient of the input current.

yes.

 

[n1cm0c]

I think that you are seeing several problems.

One of them is possibly mismatch. The input of the mirror will not have exactly the size you manufactured it for, and any error will be multiplied by 100.
Monte Carlo could show you this, if it varies the sizes and model parameters of individual devices, and not multiples.

Another one could be just the low rds, or , low output resistance. Try to regulate both the input and output to the same voltage, and see if the current ratio improves. If it does, you'll know that your output resistance is very low (which is strange...). Using min L for the bottom mirror devices is a bad idea, btw, since their rds will be low, and the cascode can only multiply what you have there. Starting with a low value makes things more difficult...

Keep the current high enough so that the overdrive of the input devices is 0.4 volts. If you reduce the current you'll have several things changing together (mismatch , gm*ro of cascode, rds of mirror).

The temperature coefficient points to a degenerated transistor at the output, I think.

Since you have 100x more current there, are you sure that your contact resistance is 100x lower ? I would guess that there's a significant resistance in series with the source of the mirror, and that this is also reducing the effective current copying factor because of the degeneration. At the same time it would introduce a temperature coefficient, since the effective gm at the output now depends on a negative feedback loop with relatively low loop gain.

There are other layout errors that may worsen the mirroring, but it's worth checking out the easy stuff first. the M=3 and M=300 at the output do not look like a problem to me, by itself. M=1 and M=100 would not change the fact that any error at the input will be magnified 100 times at the output.

BTW, don't forget leakage currents. if you raise the temperature your junctions will leak a lot mor ecurrent. Are you using a poly resistor for your filter, or a well resistor?

Hope this helps!

Added after 3 hours 29 minutes:

BTW, I forgot to add, you have such a large nmos as a decoupling capacitor!
Did you check if your process has gate leakage current ? At 0.5um this should not
be a problem yet, and it should appear in the simulations, if it's modeled.
Another problem that may arise out of this large surface of silicon are *pinholes* in the gate. If there's one then you'll have a voltage drop across your resistor,
bringing down the vgs of the output device, and this will appear at the output amplified by the mirroring ratio.

Short out the resistor with FIB and you can check for this.

 

[hung_wai_ming@hotmail.com]

Hi jiesteve,

Do u think m=3 can be easily matched in layout compared with an even number and also how can u match m=1 to m=3 and m=100?
if you think it can be matched very easy, then i have no problem with this arrangement.

 

[ch1k0]

Top (cascode) devices not have to match any of bottom (mirror). M=1 to M=100 has bad match because mismatch M=1 is much more than M=100. M=1 in chip not equal to M=1 of simulation, Vth and Beta have mismatch. M=100 have less mismatch, much larger area.

Match of M=3 is better, not much, but some. More area, more match. M=300 have less mismatch. if transistor is same, more is better, copy of current is good.

 

[Fom]

Mismatch will cause random deviation around 100:1.
But if I understand right chang830 is talking about systematic error 80:1 instead of 100:1.

 

[scottieman]

hi,
Pls. take a look at the attached diagram of a current mirror.

This is a 1:100 current mirror. The NMOS CAP is added here to keep the gate from rippling. In designing/simulation, it is OK. The current ratio is good for all the PVT corners.

But the silicon test is disillusionary. The ratio of current mirror have large excursion from the design value. It is about only 1:80, when the input current is samll, the ratio of current mirror is even low to 1:60.

Another interesting thing is that the ratio of the current mirror have a positive linearly temperature coeffcients.I.e, when the temperature increases, the ratio increased also. While in simulatiion, it is independed with the temperature.

Would anyone help to find any issues with my circuit?

BTW, the process is 0.5um CMOS processs.
Thanks in advance

Before I post my suggestions here, I would like to ask about measurement setup. Can you tell how you inject a current or create a current source as input ans how can you measure the output current. As inputting current and measurement current is not as trival as voltage, knowing it before making suggestions are the best way to myself.

Hope it helps
Scottie

 

[butterfish]

hi,
Pls. take a look at the attached diagram of a current mirror.

This is a 1:100 current mirror. The NMOS CAP is added here to keep the gate from rippling. In designing/simulation, it is OK. The current ratio is good for all the PVT corners.

But the silicon test is disillusionary. The ratio of current mirror have large excursion from the design value. It is about only 1:80, when the input current is samll, the ratio of current mirror is even low to 1:60.

Another interesting thing is that the ratio of the current mirror have a positive linearly temperature coeffcients.I.e, when the temperature increases, the ratio increased also. While in simulatiion, it is independed with the temperature.

Would anyone help to find any issues with my circuit?

BTW, the process is 0.5um CMOS processs.
Thanks in advance

Hi, chang830:

1> whats your supply voltage? is it lower than 2v?
2> whats the current value in your reference path? is it smaller than 1uA?
3> what kind of resistor you used in RC?
4> did all of the transistors matched in layout?

 

[122013137]

Just be may doubts for you ~ r