EDA_hg81
Advanced Member level 2
Please correct my understanding:
At the 1th clock check if the sload = ‘1’
At the 2th clock “data” are assigned to “result_reg”.
Thanks.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY count IS
PORT
(
clock: IN STD_LOGIC;
sload: IN STD_LOGIC;
data: IN integer RANGE 0 TO 31;
result: OUT integer RANGE 0 TO 31
);
END count;
ARCHITECTURE rtl OF count IS
SIGNAL result_reg : integer RANGE 0 TO 31;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (sload = '1') THEN
result_reg <= data;
ELSE
result_reg <= result_reg + 1;
END IF;
END IF;
END PROCESS;
result <= result_reg;
END rtl;At the 1th clock check if the sload = ‘1’
At the 2th clock “data” are assigned to “result_reg”.
Thanks.