A simple question for the following code:

[EDA_hg81]

Please correct my understanding:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY count IS
	PORT
	(
		clock: 		IN STD_LOGIC;
		sload: 		IN STD_LOGIC;
		data: 		IN integer RANGE 0 TO 31;
		result:		OUT integer RANGE 0 TO 31
	);
END count;

ARCHITECTURE rtl OF count IS
	SIGNAL result_reg : integer RANGE 0 TO 31;
BEGIN
	PROCESS (clock)
	BEGIN
		IF (clock'event AND clock = '1') THEN
			IF (sload = '1') THEN
				result_reg <= data;
			ELSE
				result_reg <= result_reg + 1;
			END IF;
		END IF;
	END PROCESS;

	result <= result_reg;
END rtl;

At the 1th clock check if the sload = ‘1’

At the 2th clock “data” are assigned to “result_reg”.

Thanks.

 

[aapatel374]

u r right

 

[lucbra]

wrong!!

At the rising edge of clk the resulting value of sload (either '1' or '0') will decide if result_reg gets the value data or result_reg+1.

See attachment for the result in Synplify

 

[EDA_hg81]

who is right?

I am confused.

Thanks.

 

[aapatel374]

at the rising edge & s load is 1 then result will be data & otherwise means if sload is not 1 then result will be result_reg + 1. means sload is only for the resetting the counter.