bhl777
Full Member level 6
Hi all, when I was reading Hans Camenzind's book (http://www.designinganalogchips.com/_count/designinganalogchips.pdf), I have a question at page 33. Here is what the author said
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If you place all the p-channel transistors in a common n-well, you get the smallest total area
and therefore the lowest cost. But if the source of such a transistor is operated below the positive supply, the back-gate (the n-well) pinches off the channel further and you get a reduced gain (by perhaps 30%). You can avoid this by placing this transistor in its own n-well.
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Here are my questions:
(1) why we call n-well a "back-gate"?
(2) for normal PMOS, we connect bulk with source to VCC. In this text the author mentioned, if VCC is lower than the normal value, the gain will be reduced. But the author said we can avoid this by placing the transistor in its own n-well. My question is why when a PMOS has a single n-well, its gain will not be destroyed, if its source and its n-well still connect to lower VCC.
Thank you!
---------
If you place all the p-channel transistors in a common n-well, you get the smallest total area
and therefore the lowest cost. But if the source of such a transistor is operated below the positive supply, the back-gate (the n-well) pinches off the channel further and you get a reduced gain (by perhaps 30%). You can avoid this by placing this transistor in its own n-well.
------------
Here are my questions:
(1) why we call n-well a "back-gate"?
(2) for normal PMOS, we connect bulk with source to VCC. In this text the author mentioned, if VCC is lower than the normal value, the gain will be reduced. But the author said we can avoid this by placing the transistor in its own n-well. My question is why when a PMOS has a single n-well, its gain will not be destroyed, if its source and its n-well still connect to lower VCC.
Thank you!