a question on PLL simulation

[Robertt]

Dear all,

When I simulate the transistor level PLL in spectre, I found the following problem which annoyied me for two weeks.
My PLL can lock the reference frequency but cannot lock the reference phase. The input reference frequency is 25MHz. The output clock of the divider has the same frequency but with rising(or falling) edges 650ps away from that of the reference clock. Is that accecptable? The VCO is working at 200M.

What's more, when I only simulate the VCO. I found the control voltage need 2.3V to let the VCO oscillate at 200MHz. But when I simulate the whole PLL, after the PLL is stable, the control voltage is only 1.8 V. Why?

Thanks a lot

 

[easytarget]

Hi Robert,

Your PLL is locked as long as d(ΔΦ)/dt=0, and Δω=0, so congrats. Regarding the difference in Vcontrol, this is most likely because your standalone VCO sees a different capacitance than when it is in the loop, so just follow it with the next stage to get an accurate Vcontrol.

 

[Btrend]

in my opinion,
1. u can not make a system response with no delay, unless u can predict it. that is equivalent to say : ur output clock should be later than ur reference clock. I agree with easytarget's viewpoint.
2. the VCO gain : Kvco=Δfvco/ΔVctrl should be the same in open loop and closed loop. u should check ur setting of estbench in open loop and closed loop.

 

[Robertt]

easytarget,

do you mean that we needn't let the output phase be exactly same as the reference phase even they have big difference? in this case, say 2ns is also acceptable?

 

[vale]

hi robertt,
The 2ns is acceptable.
The difference of Vctrl between the free running VCO and in a PLL may caused by the different load impedence.

 

[Robertt]

Thank all of you,

I break the loop and simulate the VCO again, now the control voltage are same for open loop and close loop