A question of CDL out

[hdqkwr]

I get the foundry model of resistor has the following form:

.subckt subname n1 n2 l=length w=width
r1 n1 n2 ...
.ends subname

But in CDL out, I can only output the following form of subckt.
such as:

.subckt subname n1 n2
r1 n1 n2 ...
.ends

So I can't use my spice model directly,I have to modify my CDL out netlist to have the same form of my spice model.How can I get the CDL out subckt has the same form of my spice model?That is,get the CDL out scbckt has the width and length include in the first line of it.Or has other means to resolve it?
Thank you very much!

 

[sunking]

have you select the option when you run the program to get the cdl? There is an option about the output is R value or W/L

The worse is you modify by manual