In a master-slave type flipflop, you have two latches with passgates which are operated(opening and closing) by clock and clock-bar. When the first latch is in the transparent mode the slave latch will be in latching mode and vice versa. Simple latch will have back to back connected inverters and a passgate. So there will be a RC delay from the data port of the master latch to the point where it reaches the gate of first inverter. This RC delay plus the time the gate takes to reach 50% level is setup time.