agump
Member level 2
calendar_m spi
Hi,
I have a question about the calendar_m in the SPI4.2 , maybe you can give some help to me.
The standard says that the FIFO status will be sent calendar_m times , and it does this in order to reduce the redundance introdued by the DIP-2 and framing pattern. But when I read some article about SPI4.2 , it seems that the FIFO status just simply repeats calendar_m times. I can't understand this. Since I have got all the FIFO's status from the first calerdar sequence , there's no need repeat it. If we repeat it, it just wasts bandwidth. What's wrong with these? please give your comments. thansk
Best regards
Agump
Hi,
I have a question about the calendar_m in the SPI4.2 , maybe you can give some help to me.
The standard says that the FIFO status will be sent calendar_m times , and it does this in order to reduce the redundance introdued by the DIP-2 and framing pattern. But when I read some article about SPI4.2 , it seems that the FIFO status just simply repeats calendar_m times. I can't understand this. Since I have got all the FIFO's status from the first calerdar sequence , there's no need repeat it. If we repeat it, it just wasts bandwidth. What's wrong with these? please give your comments. thansk
Best regards
Agump
