horzonbluz said:I set new contraints on test signals and these contraints just prevent inserting buffers in the TEST_SE and TEST_MODE nets. Why this can cause timing violations.
horzonbluz said:Hi, gerade.
I don't think your advice is right.
1. set false path can reduce the area of my design.
2. Since the test signal ports need to drive very high load in my chip, i need set driving ability zero for them.
3. If i don't set don't touch network constraint on TEST_MODE, the DC tool will insert buffers in the TEST_MODE net although the TEST_MODE net maybe has not high load.
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