A question about synthesis

[horzonbluz]

set_case_analysis

Hi, friends.
I'm a digital integrated Circuit designer.I have a question about timing in synthesis.
I synthesis a Digital circuit and find a problem in my circuits.
I have not treated the test signals as ideal signal, in the other words treat the TEST_SE and TEST_MODE nets as ideal net, and have infinite driving ability in the past. Now the P&R engineers want me to handle them as ideal nets as clock or reset signals. But there are some paths in my design have timing violation when i set new contraints on the test signals. These timing violation can't be fixed.
Why this happen? I set new contraints on test signals and these contraints just prevent inserting buffers in the TEST_SE and TEST_MODE nets. Why this can cause timing violations.

 

[gerade]

set_dont_touch_network

do you recompile it? from compilation and then dft compilation

do you use both set_dont_touch_network
and set_ideal_network?

show us what did you do and your constraints

 

[AlexWan]

set_case_analysis synopsys

I set new contraints on test signals and these contraints just prevent inserting buffers in the TEST_SE and TEST_MODE nets. Why this can cause timing violations.

Hi,horzonbluz

Could you tell us your new contraints on the Test pins? and What is your tools , DC, BG or others?

Synopsys apply the TetraMAX for DFT, and the BG support the DFT direct, and need to modify the script extensive.

 

[horzonbluz]

set_case_analysis constant high

I didn't both set ideal net and don't touch network constraints on the test signals, and more i use the DC2003.06 UNIX vesion to synthesis my design. When i added new contraints, i resynthesis my design. These are constraints that i added for the test signals:
set_false_path -from TEST_SE;
set_false_path -from TEST_MODE;

set_drive 0 TEST_MODE;
set_drive 0 TEST_SE;

set_dont_touch_network TEST_SE;
set_dont_touch_network TEST_MODE;

hookup_testports -verbose;

 

[gerade]

set_case_analysis usage

1.I think this 2 should be remove
set_false_path -from TEST_SE;
set_false_path -from TEST_MODE;

2.and choose one smallest buf in your lib instead of using 0 for drive

3. if your test_mode doesn't have high fanout
remove set_dont_touch_network TEST_MODE;

and try again then tell us your result

 

[horzonbluz]

set_ideal_network propgate

Hi, gerade.
I don't think your advice is right.
1. set false path can reduce the area of my design.
2. Since the test signal ports need to drive very high load in my chip, i need set driving ability zero for them.
3. If i don't set don't touch network constraint on TEST_MODE, the DC tool will insert buffers in the TEST_MODE net although the TEST_MODE net maybe has not high load.

 

[gerade]

propagate set_case_analysis

1.about false path, if one path is not false path, you should not set it
make sure that if they are really false path with the designer. contraints should be consistent with your design's fuction

2. if you set ideal network and don't touch for scan_mode it will not generate buffer. so it doesn't matter which cell you choose. sorry to this

3.you are right, when test_mode has high fanout

4.one case i forget to ask,
do you use test_mode to choose test_clk and functional clock in your design
if so, use
"set_case_analysis test_mode 0 "

in your constraints file

regards

 

[horzonbluz]

set case analysis in dc_shell

Hi, gerade. My friend.
Your 2rd advice maybe right.
But the fourth advice may not right. The set case analysis constraint is used in PT, can you sure it can be used in DC? Of course the Test_mode is used to choose test_clk and functional clock.

 

[sandusty]

set case analysis synopsys

1. Set ideal net in synthesis
2. Run pre-sim with ieadl net delay (with your synthesised gate level ckt)
3. Pass down your constrains (on those testing signal) to the P&R engr. than those testing signal will be taken care in tools
4. Run STA, with SDF, on the P&R generate ckt
5. Run post-sim on gate level with SDF and the net ckt generated by eack-end

The constrains for P&R should be different from the synthesis on those nets... otherwise, back-end tools will never know your timing requirements....

 

[gerade]

question for synthesis

sorry for slow reply,

i am quite sure about that, actually we use this for syntheiss.

reason is that, DC only does kind of rough synthesis for our design. which will be further refined in P&R tools.
set_case_analysis test_mode 0 is to ask DC only to concentrate on normal function and leave the test mode to P&R tools. as this case is not so critical, it can be handled easily in P&R tools.

in pt you will use set_case_analysis for both case to check if P&R result meet the timing requirement.

regards

 

[horzonbluz]

set_case_analysis vs set_false_path

Hi, my friend gerade. I never use set_case_analysis in DC and never see any manuals mention this.
Can you give me some data about use set_case_analysis in DC?

 

[gerade]

valid case analysis set

just run man set_case_analysis in dc_shell

 

[horzonbluz]

set_case_analysis ets cadence

:wink:
Hi, gerade.
I have set new contrtaints on test signals and resysthesis my design.
The result is satified. The timing violations and area are all redued.
I think set_case_analysis is better than set_false_path to tell DC tool hadling the test signals.

 

[bendrift]

case analysis dc_shell

can anyone tell me how the set_case_analysis act on the timing analysis?
i saw that some article said that dc cann't use set_case_analysis, is it right?

 

[no_mad]

synthsis ideal net

Hi bendrift,

The ans for your question is set_case_analysis propagates the constant forward through the netlist and it automatically disables the appropiate timing arcs based on the logic constant. Also, it does not remove logic

This answer I saw it in solvnet by synopsys.

Hope it helps

 

[haosg]

synthesis set_case_analysis

you should set_case_analysis 0 TEST_MODE in functional STA,
and set_case_analysis 1 TEST_MODE in test mode STA.

 

[cnspy]

effect of set_case_analysis on synthesis

Hi, gerade.
I don't think your advice is right.
1. set false path can reduce the area of my design.
2. Since the test signal ports need to drive very high load in my chip, i need set driving ability zero for them.
3. If i don't set don't touch network constraint on TEST_MODE, the DC tool will insert buffers in the TEST_MODE net although the TEST_MODE net maybe has not high load.

Why it will reduce the area?