A question about ring differential oscillator

[incol]

the fig is one of the delay cells, I meet a problem: when the voltage of node 8 became the highest, the voltage of node 9 is not the lowest, two voltage waveforms are not symmetry. And the current of M24 is not constant, it also oscillate. what is the reason??

 

[Btrend]

in my opinion,
1. the current of M24 should not oscillate. u had to check node 2 & 4 they must be oscillated too. otherwise u had check M5 & M24 , they must be not in saturation region, such that this cascode transistors can not provide a high resistance to the differential pair.
2. adding a cap (large enough, 10~20pF)at node 2 to remove feedthough noise from differential pair.
3. the size of MOS seems not reasonable.

 

[incol]

in my opinion,
1. the current of M24 should not oscillate. u had to check node 2 & 4 they must be oscillated too. otherwise u had check M5 & M24 , they must be not in saturation region, such that this cascode transistors can not provide a high resistance to the differential pair.
2. adding a cap (large enough, 10~20pF)at node 2 to remove feedthough noise from differential pair.
3. the size of MOS seems not reasonable.

I check node 2 &4, node 4 is oscillated, node 2 didn't change. BUt I don't think node 4 oscillated is wrong. I see from the Razavi's book <Design of Analog CMOS Integrated Circuits>, in chapter 14 the waveform of Vp(node 4) is oscillated.
And could you tell me what wrong about the size of MOS.
thanks!!

 

[Btrend]

1. if the cascode bias current is function o.k., then it is surely equivalent to a high resistance, such that the oscillate at node 4 will not effect the current drain from the cascode bias current. But there exist CGDO of M24 which will pass ripple at node 4 to node 2 (feedthrough). and if node 2 is not constant, the resistance of the cascode bias will varied, such that ur bias current is varied too.
2. But u had checked node 2 as a constant voltage, so there is no other reason (except the channel lenght modulation) for the current bias to varied if and only if the bias voltage (node 2 & 3) are correct biased .
3. what I mentioned is that the size of current mirror are too large as compared to ur differential pair. How could u place them together such that matching error between delay cells are small ? otherwise, different delay time (phase delay) between cells exist, and this is another asymmetry property.
4. what application or frequency range u made this oscillator ?
5. by the way, if u expect node 9 to be "lowest level"= 0, then another asymmetry is introduced, cause the nmos load (M3, M4) are not a linear resistance

 

[incol]

1. if the cascode bias current is function o.k., then it is surely equivalent to a high resistance, such that the oscillate at node 4 will not effect the current drain from the cascode bias current. But there exist CGDO of M24 which will pass ripple at node 4 to node 2 (feedthrough). and if node 2 is not constant, the resistance of the cascode bias will varied, such that ur bias current is varied too.
2. But u had checked node 2 as a constant voltage, so there is no other reason (except the channel lenght modulation) for the current bias to varied if and only if the bias voltage (node 2 & 3) are correct biased .
3. what I mentioned is that the size of current mirror are too large as compared to ur differential pair. How could u place them together such that matching error between delay cells are small ? otherwise, different delay time (phase delay) between cells exist, and this is another asymmetry property.
4. what application or frequency range u made this oscillator ?
5. by the way, if u expect node 9 to be "lowest level"= 0, then another asymmetry is introduced, cause the nmos load (M3, M4) are not a linear resistance

This oscillator's frequency is 48MHZ, and I want its frequency not to change when temperature change from -40 to 125 and vcc change from 2.4v to 5.5v. So I use PATA current as its biase current. I found that only PATA current increased from 110ua to about 220ua that frequency won't changed, but the current is too large, and the size of MOS had to be set very large. If I reduce the current, the current will increase smaller as temp changes(.i.e. the current is 20ua at -40, then it only increases 18ua at 125), so I want to find other method to solve this problem.

 

[adam79416]

yes , u r right.

Added after 1 minutes:

M24 is in the wrong . u should check the bisa voltage