Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A question about process corner.

Status
Not open for further replies.

holddreams

Full Member level 6
Joined
Aug 2, 2005
Messages
351
Helped
15
Reputation
30
Reaction score
7
Trophy points
1,298
Location
Shanghai
Activity points
4,237
process corner

I designed a folded-cascode opamp, and ran the simulation in tt_corner.
One of the MOS Ids=13uA, but when used ff_corner(other parameters not changed,only replace tt_corner by ff_corner), then Ids changed to 29uA, so large!
And when using ss_corner, this MOS cutoff!

How should I do?

Thanks.
 

ccw27

Full Member level 5
Joined
Oct 13, 2004
Messages
267
Helped
14
Reputation
28
Reaction score
6
Trophy points
1,298
Activity points
2,558
Thats right ! You need to make your design more robust against process variation. A good voltage bias generator may help you in this case. How are you biasing your cascodes? A good bias can help track the process variation.

Good luck
 

holddreams

Full Member level 6
Joined
Aug 2, 2005
Messages
351
Helped
15
Reputation
30
Reaction score
7
Trophy points
1,298
Location
Shanghai
Activity points
4,237
I guess ,it may be because of the process model.
I did a test,just use a NMOS transistor ,whose source and bulk were connected to ground, and gave the gate a vin=3.3v, v(drain)=3.3v, then run .op,
and in the .lis file ,the Id change about 15% about tt_corner and ff_corner.
But if when vin=1.1v, v(drain)=3.3v, then the Id changed about 100% about tt_corner and ff_corner.
 

allan_guo

Junior Member level 3
Joined
Jan 6, 2006
Messages
28
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,283
Activity points
1,555
holddreams said:
I guess ,it may be because of the process model.
I did a test,just use a NMOS transistor ,whose source and bulk were connected to ground, and gave the gate a vin=3.3v, v(drain)=3.3v, then run .op,
and in the .lis file ,the Id change about 15% about tt_corner and ff_corner.
But if when vin=1.1v, v(drain)=3.3v, then the Id changed about 100% about tt_corner and ff_corner.

what do you mean "because of the process model"?
Let's assume vth=1v(tt) vth=0.9v(ff) then
when vin=1.1v Vgs-Vth=0.1(tt) 0.2(ff);
but when vin=3.3v Vgs-Vth=2.3(tt) 2.2(ff);
so you can see why when vin is low the change ratio is large.
 

paulux

Advanced Member level 4
Joined
May 16, 2005
Messages
112
Helped
11
Reputation
22
Reaction score
2
Trophy points
1,298
Activity points
2,339
Please use ideal current source for check your biasing.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top