a question about PLL noise in high speed digital circuit.

[chmhero]

i want to design a spread sptrum PLL which provide 800MHz clock for digital circuit .
PLL power supply is a independent analog power supply differ from another circuit .and how about the power supply noise ,is it clean ??? . some papers mention that power supply noise is one of the most important noise source effect on phase noise . PLL ground is also independent ground ,how about the the substrat noise . any suggest is welcome .

 

[qslazio]

I think you should seperate the power supply for PFD DIVIDER and other analog part.
Because the analog parts are supply noise sensitive.

PFD and DIVIDER will induce the Fpfd or other freqeuncy noise on your power supply, and your output PSD will have the spur.

 

[chmhero]

Re: a question about PLL noise in high speed digital circuit

thanks .qslazio
the pdf and diveder use different power supply . it is mean that we can overider the power supply noise of VCO ? thanks ?

 

[qslazio]

VCO has a lot of noise source.
But as for the supply noise, I think you should increase the PSRR of voltage buffer between Low pass filter and VCO. That is where power supply noise injected into VCO.

And pay much attention to the supply you use for your Level Shift after the Ring Oscillator. This supply will also induce jitter. What you need to seperate is this supply.

 

[montage2000]

VCO CP use seperated VDD

 

[fashion]

seperate vco power and power of digital part will improve the performance of vco.

 

[montage2000]

substrate noise is hard to isolated, except deep well

 

[hanjiemy]

1. Sperate power supply of VCO, CP, Divider.
2.Maybe add a Regulator to VCO's power. (Decrease pushing)
3. Add a lot of decoupling cap between vcc and gnd.
4. Add guard ring for each cell in layout.

hope it's useful!

 

[hackjiang]

Re: a question about PLL noise in high speed digital circuit

If you care more about noise, useing LC tank instead of Ring Oscillator.