a question about delay difference

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ustc23

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A,B,C is 8bit integer，Z=A*B，Z=A*B+C，pls compare the delay difference between two designs，in unit of gate（e.g.：the difference is 4 Full Adder + 1 MUXs）
pls explain the result in detail
Thank you!
 

The area saving methord may different just in a level of 3->2 Wallace tree(the name may wrong). The MUL design is usually booth encoding + wallace tree + a final adder. You can search more info on MUL design to know more about it.
 

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