kequal
Newbie level 3
We've developed a DDR memory controller in Xilinx FPGA. The waveform of the control signals from FPGA to DDR memory seem to accord with the specification well, but the datas read from the memory ofen do not equal to the ones been written to it.
Did anybody has any experiences about such situation?
BTW, the voltage of the DDR memory is not quite good. It has a +/-100mv shift. Is this the reason for that?
Did anybody has any experiences about such situation?
BTW, the voltage of the DDR memory is not quite good. It has a +/-100mv shift. Is this the reason for that?