Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A problemn about Berkeley Thomas cho's PHD about ADC

Status
Not open for further replies.

gdhp

Advanced Member level 4
Joined
Jan 7, 2005
Messages
116
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,298
Activity points
931
thomas cho berkeley

In the phd paper of Thomas cho's ADC, page 100.

He said large error correction range can eliminate the dedicated input S/H circuit. And

the input signal can be sampled simutaneously by switched capacitor amp and dynamic

comparatorof flash A/D.

How to understand this? Then he give a input band limite range for input.

Two quesitons:
1. Why large error correction range can eliminate the need of input S/H circuit? What is

their relations?

2. Because no S/H circuit, so there is an input bandwidth range. As the fomular gives?

Thanks!

Attach is the phd paper!
 

Hi
If signals changes less than 1 LSB (LSB of first GS) in interval between end of sampling and beginning of comparator decision, we can remove S/H circuit.
so I think
dV/dt<1 LSB/Tinterval
V=a sin(2pi*f)
a*2pi*f< 1 LSB/Tinterval
f<1 LSB/(Tinterval*2pi*a)

I'm not sure
this is just my opinion.
regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top