NO1_NANO
Newbie level 4
Now I face a problem when using the Vncap to consist of a 6*6 cap array.
I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I use a array of vncap, for example 6*6 , the LVS error is
"multiVPPcomp has mismatched parameter(s):"bp" layout: 0 schematic: 3".
So can anyone help me to solve the problem. Thanks.
ps: I use IBM library: cmrf8sf.
I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I use a array of vncap, for example 6*6 , the LVS error is
"multiVPPcomp has mismatched parameter(s):"bp" layout: 0 schematic: 3".
So can anyone help me to solve the problem. Thanks.
ps: I use IBM library: cmrf8sf.