superleaf
Junior Member level 3
The layout have passed the DRC and LVS in Cadence simulation platform,and then I made a calibre PEX simulation to extract prasitic resistance and capacitance,in the extracted schematic,i found something weird,the number of MOS is more than the mos in the original schematic,for example,if the finger of the MOS is 4,the number of the this kind of MOS is 1 in the original schematic,then in the extracted schematic,the number of this kind of MOS become 4*1=4,and current Id which run through the MOS also change after extraction!so strange!!I don't know what is the problem is?Anyone who have encountered the problem like this?Appreciate your help!