Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] A problem in VHDL- signal assigned to one pin of a component

Status
Not open for further replies.
A

ahmadagha23

Guest
A problem in VHDL

Hi;
I assigned a signal to one pin of a component in top-module. in defining of that component I initialized that pin to '0'.
by default that pin is defined as "inout" type. While simulating in top module when the value of signal should change to "1", it changes to "X". When I change the type of that pin to "in" type it works true. I want to use that pin also as out, so I should use it as "inout". In fact it is a side of a bidirectional buffer.
Would you please guide me? my code is in VHDL.

Regards
 

kvingle

Full Member level 5
Joined
Nov 5, 2007
Messages
244
Helped
33
Reputation
66
Reaction score
12
Trophy points
1,298
Location
India.
Activity points
2,576
Re: A problem in VHDL

While writing in HDL always try to visualise what your code going to yield in synthesis.

For a bidirectional signal which can drive and can be driven there should some other control signal which specifies when to act as input and when as output.if you dont have such signal then what you will see as 'X' because there will be two drivers for same signal.( one from inside your design and other from outside.)




here is a nice example of typical tristate buffer.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe, clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;

ARCHITECTURE maxpld OF bidir IS
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
-- value from input.
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
BEGIN -- feedback value.
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
a <= inp;
outp <= b;
END IF;
END PROCESS;
PROCESS (oe, bidir) -- Behavioral representation
BEGIN -- of tri-states.
IF( oe = '0') THEN
bidir <= "ZZZZZZZZ";
b <= bidir;
ELSE
bidir <= a;
b <= bidir;
END IF;
END PROCESS;
END maxpld;
 

A

ahmadagha23

Guest
Re: A problem in VHDL

I construed the reason: for inout ports, there is an internal and an external drivers which work independently. So you should determin for each of the internal and external states their values and these values should not have conflict. For example when I added the assignement of 'Z' value in internal code for state that inout pin should be drived by external value it worked truely.
process (clk_DIRn,aclk,bclk)
begin
if (clk_DIRn='1') then
aclk <=bclk after Tbuff+Tcable+Tbuff;
bclk <= 'Z';
elsif (clk_DIRn='0') then
bclk <=aclk after Tbkp;
aclk<= 'Z';
end if;
end process;

regards
 

kvingle

Full Member level 5
Joined
Nov 5, 2007
Messages
244
Helped
33
Reputation
66
Reaction score
12
Trophy points
1,298
Location
India.
Activity points
2,576
Re: A problem in VHDL

Is your problem solved?
which is your bidirectional signal?
 

A

ahmadagha23

Guest
Re: A problem in VHDL

yes it solved. both aclk and bclk are bidirectional. u can consider only one of them.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top