A
ahmadagha23
Guest
A problem in VHDL
Hi;
I assigned a signal to one pin of a component in top-module. in defining of that component I initialized that pin to '0'.
by default that pin is defined as "inout" type. While simulating in top module when the value of signal should change to "1", it changes to "X". When I change the type of that pin to "in" type it works true. I want to use that pin also as out, so I should use it as "inout". In fact it is a side of a bidirectional buffer.
Would you please guide me? my code is in VHDL.
Regards
Hi;
I assigned a signal to one pin of a component in top-module. in defining of that component I initialized that pin to '0'.
by default that pin is defined as "inout" type. While simulating in top module when the value of signal should change to "1", it changes to "X". When I change the type of that pin to "in" type it works true. I want to use that pin also as out, so I should use it as "inout". In fact it is a side of a bidirectional buffer.
Would you please guide me? my code is in VHDL.
Regards