a problem about the simulation of varilog-A using spectre!!

the error is listed below ,who can give me a advice about that ? thanks first!!


Command line:
/tools/IC5/tools.lnx86/spectre/bin/spectre -env artist5.0.0 \
+escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre1_18652_1 -format psfbin -raw ../psf \
input.scs
spectre pid = 18970

Loading /tools/IC5/tools.lnx86/spectre/lib/cmi/3.0/libinfineon_sh.so ...
Loading /tools/IC5/tools.lnx86/spectre/lib/cmi/3.0/libnortel_sh.so ...
Loading /tools/IC5/tools.lnx86/spectre/lib/cmi/3.0/libphilips_sh.so ...
Loading /tools/IC5/tools.lnx86/spectre/lib/cmi/3.0/libstmodels_sh.so ...
spectre (ver. 5.0.33.092203 -- 23 Sep 2003).
Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
Security, Inc.

Simulating `input.scs' on mazhe at 12:44:19 PM, Wed Jul 27, 2005.

Warning from spectre during circuit read-in.
"input.scs" 13: Illegal unit prefix `v' ignored.
"input.scs" 13: Illegal unit prefix `v' ignored.
"input.scs" 15: Illegal unit prefix `V' ignored.
"input.scs" 15: Illegal unit prefix `V' ignored.
"input.scs" 17: Illegal unit prefix `v' ignored.
Further occurrences of this warning will be suppressed.
Error found by spectre during AHDL read-in.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 41:
"parameter real center_freq=10MEG;<<--? "
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 41:
Error: syntax error
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 41:
Error: illegal declaration.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
"triangle = idt(integ_dir*(center_freq <<--? + vco_gain*V(2.0-vin)),
0);"
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
Error: undeclared symbol: center_freq.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
Error: right operand of type node not supported for operator `-'.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
Error: Improper use of access function.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
Error: right operand of type *undef* not supported for operator `*'.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 64:
Error: left operand of type *undef* not supported for operator `+'.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 66:
"freq = center_freq <<--? + vco_gain*V(2.0-vin);"
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 66:
Error: undeclared symbol: center_freq.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va", line 66:
Error: right operand of type node not supported for operator `-'.
"/home/mazhe/eda/cadence/pll/dig_vco_v/veriloga/veriloga.va"