will_tp
Newbie level 3
cml divider
I use CML divider to generate quadrature signal.
Should the input clock to CML be fully differential?
A group of digital divider outputs "clk" and "clkb" just is inverse of "clk".
If using "clk" and "clkb" as CML input, what problem will be have?
I use CML divider to generate quadrature signal.
Should the input clock to CML be fully differential?
A group of digital divider outputs "clk" and "clkb" just is inverse of "clk".
If using "clk" and "clkb" as CML input, what problem will be have?