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A problem about capacitor voltage divide

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May 1, 2022
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I'm currently designing CDAC. I have some questions about capacitor voltage division.
In Figure 1, this is the test bench for simulating capacitive voltage division. All capacitors are ideal capacitors with a capacitance of 1pF.
Figure 2 shows the waveforms of VO and VO2. I would expect VO and VO2 to be about 1/2*VREF, but the voltage will drop over time.
Here are my questions :

Q1. Is it the leakage of the mos switch that causes the VO to drop over time?

Q2. I'm using an ideal switch (W0 and W1, please refer to Figure 1) with an Open switch resistance of about 1T Ohms and a Close switch resistance of about 1 Ohms.

Why does the voltage of VO2 still drop over time? (My opinion is, an ideal switch has no leakage and the voltage VO2 should not drop over time)

Thank you in advance

Figure 1.PNG


  • Figure 2.PNG
    Figure 2.PNG
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  • Figure 3.PNG
    Figure 3.PNG
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this is caused by your SPICE program, as it usually introduces some conductance at different nodes to ease computation. In LTspice, this parameter is called gmin [1], which adds a cunductance to everey PN junction. It is obvious that no semiconductor is involved in an ideal capacitor scenario, so here it seems the conductance is also added for every node towards GND, "... loosely speaking, this adds and steps conductances across PN junctions and/or from every node to ground ... " [2]. Unfortunately, the LTspice documentation is not that good.

Below you can see the influence of gmin on your simple circuitry, for four different gmin settings. From your snapshot it looks like you are using Cadence Virtuoso, which I'm not familiar with, but it has for sure some similar setting, have a look at your settings menu.

The question is what are you aiming to achive? A capacitive voltage divider will never lead to a well defined voltage ratio in a reald world scenario without trimming/adjustment. Thus, high valued resistors are usually placed in parallel.




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