Hi,
this is caused by your SPICE program, as it usually introduces some conductance at different nodes to ease computation. In LTspice, this parameter is called
gmin [1], which adds a cunductance to everey PN junction. It is obvious that no semiconductor is involved in an ideal capacitor scenario, so here it seems the conductance is also added for every node towards GND, "...
loosely speaking, this adds and steps conductances across PN junctions and/or from every node to ground ... " [2]. Unfortunately, the LTspice documentation is not that good.
Below you can see the influence of
gmin on your simple circuitry, for four different
gmin settings. From your snapshot it looks like you are using Cadence Virtuoso, which I'm not familiar with, but it has for sure some similar setting, have a look at your settings menu.
The question is what are you aiming to achive? A capacitive voltage divider will never lead to a well defined voltage ratio in a reald world scenario without trimming/adjustment. Thus, high valued resistors are usually placed in parallel.
[1]
https://www.ltwiki.org/LTspiceHelp/LTspiceHelp/_OPTIONS_Set_simulator_options.htm
[2]
https://groups.io/g/LTspice/message/118250
BR