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a piece of code - synthesizeable or not?

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mawais

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Synthesizeable or not?

Hi!
I am new to VHDL, I want to know that is the following piece of code synthesizeable or not

process (x)
begin
if(x' event and x = '0') then
.....
....
end if;
end process;

Where x is any signal or input other than the clock. I am perticularly refering to the event statement that is it possible to syntesize an edge trigreed process asynchronously in a real time hardware.
I am using Xilinx ISE 10.1. Can anyone tell how to know by using this software that which part or statement is not synthesizeable.
Thanks in advance.
best regards,
Muhammad Awais.
 

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