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A ldo compensation problem

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dahuangpeng

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I have design a PMOS ldo, and have a cascode compensation. This compensation could make the second pole biger about gm*Rout,which Rout is the impendence of op
output, but when I simulate the ldo, I found the second pole is smaller than miller compensation. why it is hanpend, do anyone know it.
 

dick_freebird

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Operating at very low load current makes Rout huge and
the "load pole" frequency very low. This is one of the worse
challenges in compensating a PMOS LDO, the external
variability. Many LDOs specify a minimum load current and
some add a weak Class B / AB pulldown to make things
manageable.
 

KlausST

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Hi,

Just a question on this...
When I don't want to waste power by the "minimal load", is it possible to use a series RC combination?
The idea is that the C blocks the DC current flow, but the R forms a ohmic AC load at high frequencies.

Klaus
 

erikl

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The idea is that the C blocks the DC current flow, but the R forms a ohmic AC load at high frequencies.

Good idea, Klaus!

This is a well-known LDO compensation method, used in several variants, first published by Rincón-Mora in 2000 (I believe). Later often called Nested Miller Compensation with feedForward Gm stage (NMCF). Here's a container with corresponding URLs: View attachment Weblocs.zip
 

dick_freebird

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I think the problem is compound. There is the simple output
RC at low gDS on the pass transistor, but I believe there is
also the "gm-C filter" behavior of that pass transistor when
it is being operated well below gm-peak. And both of these
respond to output current position.

My point here, I guess, is that a capacitor-blocked resistor
is not going to affect DC drain current position, or its pushed-
back effect on pass FET gm(OP).

But a resistor-limited output cap sure looks a lot like the
particular-ESR guidance that accompanies many LDOs.
 

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