Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A ldo compensation problem

Not open for further replies.


Newbie level 5
May 14, 2015
Reaction score
Trophy points
Activity points
I have design a PMOS ldo, and have a cascode compensation. This compensation could make the second pole biger about gm*Rout,which Rout is the impendence of op
output, but when I simulate the ldo, I found the second pole is smaller than miller compensation. why it is hanpend, do anyone know it.

Operating at very low load current makes Rout huge and
the "load pole" frequency very low. This is one of the worse
challenges in compensating a PMOS LDO, the external
variability. Many LDOs specify a minimum load current and
some add a weak Class B / AB pulldown to make things


Just a question on this...
When I don't want to waste power by the "minimal load", is it possible to use a series RC combination?
The idea is that the C blocks the DC current flow, but the R forms a ohmic AC load at high frequencies.


The idea is that the C blocks the DC current flow, but the R forms a ohmic AC load at high frequencies.

Good idea, Klaus!

This is a well-known LDO compensation method, used in several variants, first published by Rincón-Mora in 2000 (I believe). Later often called Nested Miller Compensation with feedForward Gm stage (NMCF). Here's a container with corresponding URLs: View attachment

I think the problem is compound. There is the simple output
RC at low gDS on the pass transistor, but I believe there is
also the "gm-C filter" behavior of that pass transistor when
it is being operated well below gm-peak. And both of these
respond to output current position.

My point here, I guess, is that a capacitor-blocked resistor
is not going to affect DC drain current position, or its pushed-
back effect on pass FET gm(OP).

But a resistor-limited output cap sure looks a lot like the
particular-ESR guidance that accompanies many LDOs.

Not open for further replies.

Part and Inventory Search

Welcome to