Hi,
First of all P and N transistors in CMOS designs for digital ckts cannot have the same W/L ratios, ie, the transistor cannot or should not be symmeterical. This is because of the mobility difference in P and N transistors. N transistors have higher mobility than P and so to offset this difference, the P transistor is always designed at least 3 times larger than the N transistor. This will give you equal rise and fall times or equal voltage swings from HIGH to LOW.
Secondly, if you reduce the VDD of a digital circuit, it will still work as designed, but the output voltage swing will be lower, ie, you will not get full +3V (VDD) swing for logic 1, etc. You cannot keep on decreasing the VDD of a transistor below a certain level as this voltage is what sets up the electric field in the MOS that is responsible for the proper formation of the channel.
If Vdd is reduced too low, the channel will not get formed properly leading to poor functioning of the device.