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A basic CMOS Vt question!!

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mike_bihan

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cmos vt

It may be too simple,even naive. However, many of my colleague can not explain it for me.
The story is the if we connect a nmos in such way:

Drain=8v
Source=1.8v
Gate=1.8v
Bulk=0v

Will there be current ?

According Vgs>Vt formula, we will got answer "No". Simulation of Hspice agrees with this idea.
However, in almost all books, the formation of channel is discussed under the assumption that
the source are connected to the ground. Then Vgs equals to Vgb actually.

When Vs does not equal to Vbulk, it is described as body effect. The complex formula does not give
direct impact on the results.

If we analyze the problem in another way: The potential difference between the gate and the substrate will
cause concentration of the electron underneath the gate-poly. Why the inversion layer conduct current?

One of my possible explanation is that the voltage on the source and drain node are even higher than
gate-poly, therefore the electron will concentrate much more on the diffusion area, therefore the channel is
greatly weak. In other words, that the electron were pulled to the higher potential area: the drain and source.

Is that correct?

I am not good in Device Physics very much, thanks!
 

tlihu

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vt cmos

My explanation is:

Since this is an nmos device, the bulk is p-type while source/drain are n-type. If Vs/Vd are higher than Vb, the device is more deeply into depletion. Thus the channel is more difficult to form. :p

Comment?
 

tlihu

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basic cmos connection

My explanation is:

Since this is an nmos device, the bulk is p-type while source/drain are n-type. If Vs/Vd are higher than Vb, the device is more deeply into depletion. Thus the channel is more difficult to form. :p

Comment?
 

byron

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drain is at higher potential than source in nmos

when you simulate with hspice, the model you used is also important. in other words, body effect makes the mosfet more difficult to turn on.
 

mike_bihan

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what is vt cmos

yeah. I agree that body effect make the mosfet more difficult to turn on.
Do you agree with my explanation on why "body effect make the mosfet more difficult to turn on "?
 

mike_bihan

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fz140e cmos vt

tlihu said:
My explanation is:

Since this is an nmos device, the bulk is p-type while source/drain are n-type. If Vs/Vd are higher than Vb, the device is more deeply into depletion. Thus the channel is more difficult to form. :p

Comment?
Why nmos is more difficult to turn on if it is more deeply into depletion?
 

byron

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bulk,drain ,source,gate in cmos

I think your explanation is correct. My explanation is that the reverse bias on the source-to-substrate junction reduces the amount of charge in the channel for a given gate-to-source bias. Alternatively stated, it increase the gate voltage needed to induce a given number of mobile carriers in the channel, that is, it increase the threshold voltage. so it is more difficult to turn on the mosfet when taking body effect into account. By the way, in integrated circuits, we should consider the mosfet as a five terminal device: drain, source, gate, substrate, and the bulk.
 

mike_bihan

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vt an vsb in cmos

Thanks!

You are especially correct in Trip-well precess.
 

sutapanaki

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inversor cmos vt

Yes, basically the bulk and substrate are the same thing if the transistor is not in its own well - like PMOS. Then the well in which the pmos is made is the bulk and the substrate is the substrate of the chip.
As to the original post - it was more or less explained already. With this connection of the terminals of the transistor, it should not conduct current. Source-bulk and drain-bulk are p-n junctions, bulk being the p-type. The voltages show that these junctions are reversed biased. The voltage difference between gate and bulk is high - enough to deplete the area under the gate and probably also invert it. But the purpose of the channel is to connect the source and drain regions and provide means for the current to flow. That means that the potential of the area right at the source side and also at the drain side should be high enough so source-bulk and drain-bulk voltage difference is such that these p-n junctions are forward biased. These will allow electrons to move from the source to the drain through the channel. If there is a difference between the potential of the source and bulk, then this p-n junction is more into the reverse biased condition and that's why a bigger gate voltage is needed in order to even just forward bias the source channel (or source-bulk for that matter) junction - hence higher threshold voltage. Actually that's what happens fundamentally when the transistor enters in saturation - the drain voltage becomes high enough so that the voltage difference between the gate and the drain becomes Vt or smaller and the channel can not be supported anymore, so it pinches-off.
 

byron

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vt mos device

substrate and bulk are different, you can check it in any book about a typical nmos or cmos process.
 

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