8 bit ADC INL problem - help needed

[levyjj]

inl 14-bit adc

Hello all!

I design a 8 bit SAR ADC. 4 MSB bit use binary weighted capacitors, 4 LSB is R-2R ladder. simulation result is OK. But evaluation result is bad. 3 MSB have INL problem.
evaluation result: INL
0010 0000 -0.3 LSB
0100 0000 -0.67 LSB
1000 0000 -0.63 LSB
Any one can help me,please? What causes this issue? Maybe it is caused by capacitor mismatch. But capacitor relative mismatch is 1%, can it cause INL up to -0.67?
I tried to represent problem in simulation by adding mismatch, but could not get the above result.

Thank you very much!
sorry for my poor english!:

 

[ict_eda]

Re: 8 bit ADC INL problem

evaluation result: INL
0010 0000 -0.3 LSB
0100 0000 -0.67 LSB
1000 0000 -0.63 LSB
:

Here are a couple of points:
1. How is the DNL looking at the above transitions?
2. There might be something wrong with the measurement set-up. Try increasing the settling time for instance.
3. Is the evaluation result systematic or random, meaning if you measure multiple chips do you get the same INL?

Good luck,

ict

 

[levyjj]

Re: 8 bit ADC INL problem

Here are a couple of points:
1. How is the DNL looking at the above transitions?
2. There might be something wrong with the measurement set-up. Try increasing the settling time for instance.
3. Is the evaluation result systematic or random, meaning if you measure multiple chips do you get the same INL?

Good luck,

ict

Thank you very much for you reply!
1. please see the picture. I think DNL is high because of R-2R resistor layout problem.
2. I have tried to decrease RTC clock from 32KHz to 10KHz. The reuslt is same.
3. I tested 4 samples and got the same INL.

capacitors layout. capacitors labled 8C means they are paralleled to one capacitor.

 

[erikl]

8 bit ADC INL problem

Make a new layout of your cap array, which is totally symmetrical in x- and in y-direction. Use dummy caps if necessary. Surround the whole array by dummy caps of the same size. Also balance its connections.

 

[levyjj]

Re: 8 bit ADC INL problem

Make a new layout of your cap array, which is totally symmetrical in x- and in y-direction. Use dummy caps if necessary. Surround the whole array by dummy caps of the same size. Also balance its connections.

Thank you! I know layout is a problem. But I don't know whether change layout can solve INL problem. I wanted to reproduce INl problem in simualtion, but failed.
If I can not provide enough evidence, the IC will not be taped out.

 

[erikl]

8 bit ADC INL problem

A postLayout simulation (extracted netlist) should show both INL & DNL deviations. Your above values are already very good: the total error of an ideal ADC is +/- 1/2 LSB. A DNL < 1 means monotonicity, i.e. on a 1-by-1LSB stairCase input you shouldn't get a missing or a double step in the output.
The only measure to make it still more ideal is to respect best-possible symmetry at all devices which are responsible for the resolution, i.e. transistors, resistors, caps. This applies also to the periphery of these device arrays: it might be necessary to surround the edges of those arrays by dummy structures in order to guarantee homogenicity also to the border devices of the array. Always be aware that a (1 of)8LSB resolution means a max. (in-)accuracy of 0.25%, hence your layout inaccuracy must be less than this. If you have a good extraction tool, the postLayout simulation should show the result of a layout amendment.

 

[levyjj]

8 bit ADC INL problem

I understood. Thank you!