6T/8T SRAM CELL layout with row controlled VDD and VSS

[seahs]

In the LS(lithographical symmetrical) sram cell layout, vdd/vss has to be shared by the cells in the adjacent rows. I've read some papers talking about sram where the vdd is controlled row by row. I just wonder how the layout is done.

Thanks for any suggestion;-)

 

[john blue]

Try looking at this : **broken link removed**

 

[seahs]

Try looking at this : **broken link removed**

sorry but I did't find anything related...