640 byte Line Buffer

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stark43

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Hello,
I want to serialize 640 byte pixel data and I used line buffer for this and when I looked at the schematic I got scared and I think I made a mistake. Are there any nicer ways to save 640 bytes into memory? Sorry for my inexperience.
 

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stark43 said:
Hello,
I want to serialize 640 byte pixel data and I used line buffer for this and when I looked at the schematic I got scared and I think I made a mistake. Are there any nicer ways to save 640 bytes into memory? Sorry for my inexperience.
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Yes, use an actual memory (probably want to use dual-port) instead of flip-flops. You can infer a memory in RTL but the way you have written the line buffer "memory" does not allow inference of a dual port memory block. Take a look at your synthesis guides from the FPGA vendor to see how you need to write inferred memories. You might also consider using a FIFO instead as you don't appear to be accessing the memory out of sequential order.

You could also improve the final serializer, by using a shift register instead of an FSM and muxing the data to the output.

Code Verilog - [expand]
1
2

always @(posedge clk)
  out <= shift_loadn ? {out[6:0], 1'b0} : din;

out[7] is the serial output data
din is the 8-bit data to serialize
shift_loadn would be controlled by an FSM/counter logic
  1. load would be active at c0 (loads din, out[7] is din[7])
  2. shift would be active from c1-c7 (shifts din[6] to out[7], din[5]....din[0])
  3. repeat starting a 1.
Using a shift register like this will require less logic and will be capable of running at much higher clock frequencies.
 
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You're right, I really stretched the job. I have a problem. With your permission, I would like to summarize the case for you. I am interested in MIPI CSI-2 and I want to serialize it by adding some packets to parallel pixels in the simplest way without using any IP. I have a block transmitting pixels in my camera (640x512) and I convert those pixels from pixel to byte layer bytes and then save them to the buffer. Then, when prompted, I need to serially output the bytes converted by the serializer module. I'm just confused about the sync issue.
1) I want to send data as bytes to the serialization module after saving the data to the [639:0] row buffer with each pixel clk. Only the serializer will run at 200Mhz and a transmission will take 8 hours. So if I serialize the data with clk (200Mhz/8) after saving the bytes to the row buffer, will I lose data? Like this;


SVG: 
`timescale 1ns / 1ps

module serializer(
input  wire mipi_clk,                  //200Mhz     
input  wire pixel_clk,              //21,04Mhz
input  wire serial_valid ,     
input  wire [7:0] data_in,         
output reg serial_output =0
);


always @(posedge pixel_clk)
begin
    [639:0] line_buffer ---> Data is saved to line buffer
end

always @(posedge (mipi_clk / 8) )
begin
    line_buffer[0,1,2....,639] ---> Serializer
end


always @(posedge mipi_clk)
begin
    line_buffer[0] ---> As you said, we shift the data and give it to the output serially, and this process takes 8 steps.
    line_buffer[1] ---> As you said, we shift the data and give it to the output serially, and this process takes 8 steps.
    .
    .
    .
    line_buffer[639] ---> As you said, we shift the data and give it to the output serially, and this process takes 8 steps.
    
end


endmodule

Does it make sense if I do it this way sir or is the clk/8 idea nonsense? Or if I set up a combinational structure and want it to enter the serialization process as the data comes in, I think I should do it like this;

SVG: 
always @(data_in)
begin
    serialization
end

But if the same data comes in this way, I doubt that it will enter this block because there will be no change in the data. I would be very happy if you could give an idea how I can run an algorithm or logic.
 

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