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reg [63:0] r64bits;
assign a = h"0000000000000000"=r64bits ? 1'b1 : 1'b0; // comparator versus value 0x00;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 reg [63:0] a, b; wire AgtB, AltB, AeqB; // then the following does the comparison for A > B assign AgtB = a > b ? 1'b1 : 1'b0; // this compares A < B assign AltB = a < b ? 1'b1 : 1'b0; // this compares A = B assign AeqB = a == b ? 1'b1 : 1'b0;