6 layes Routing Configurations

[hot_snow]

Hello,

I have to route a 6 layers board by using the "Altium Designer 10" software.

Since it's the first time that I'm working with the multilayer technique I found a lot of problems:


Well, I decided to use this stuck-up:

1-Top Layer
2-GND
3-Signal Layer 1
4-Signal Layer 2
5-Power
6-Bottom.

Is it the best choice?

First, in my board I use 3 powers : 1.2V, 1.8V and 3.3 V. What's the considerations that I should take when I will split the plane power into 3 regions?

Sencond,in this board we have a DSP with the frequency of 600 MHz and 2 DDR; I want to know if I have to take precautions about the signal integrity, if yes what'are these precautions?

Finally, how can I chose the width value of tracks and the vias value between layers?

I know that I asked a lot of questions, but I feel that I'm a little blocked.

Any help will be appreciated...

Regards,

 

[barry]

That's a lot of questions!!! Yes, your stackup looks ok. As far as splitting your power plane, you need to be aware of what signals are above and below the planes. For instance, if you've got a digital power plane, you don't want low-level analog signals running over/under it.
Yes, you have to take precautions with your 600MHz signals; there are entire books written about what you need to do. (I've never read any of them) Several things to keep in mind: keep traces about the same length to avoid skew errors; pay attention to line impedance if these are matched signals like LVDS, etc.; minimize vias-they are discontinuities and cause reflections.
The width of the traces is determined by the required impedance; if that doesn't matter and they are not carrying a lot of current, then you can make them any size you'd like.

Hope that gives you a start

 

[loosemoose]

You should ask your board shop to give you the trace widths for the required impedance's. Most do have a calculator and also have measurements from previous customers.
The minimal trace width and vias will be set by the DSP, where you need to resolve the fan out of the chip.
Also run all you critical traces on ground plane side where you do not have splits (layer 1 and layer 3).