How about the 51 mcu bus to FPGA interface through P0 and P2 bus, I use the "register share" tech, but if the registers , the design must be complex, can you give me some suggestions on it?
How about the 51 mcu bus to FPGA interface through P0 and P2 bus, I use the "register share" tech, but if the registers , the design must be complex, can you give me some suggestions on it?