50Hz~2MHz clock generator?

[sanJerry2004]

Anybody can give me the introduction of 50Hz~2MHz clock generator chip? Step 1 Hz.
IN my original BERT design, wanna the data pattern rate from 50Hz to 2Mhz continued adjusted, and resolution 1 Hz.

 

[echo47]

A DDS would work well. Maybe these similar discussions will help you:

 

[sanJerry2004]

En, TKS. I also knew the DDS chip can do that. BTW, can we realized the function in FPGA. any comments, pls.

 

[echo47]

You can implement the digital parts of a DDS in an FPGA, but not the analog parts such as the DAC, filter, and comparator.