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50Hz~2MHz clock generator?

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sanJerry2004

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Anybody can give me the introduction of 50Hz~2MHz clock generator chip? Step 1 Hz.
IN my original BERT design, wanna the data pattern rate from 50Hz to 2Mhz continued adjusted, and resolution 1 Hz.
 

echo47

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A DDS would work well. Maybe these similar discussions will help you:
 

sanJerry2004

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En, TKS. I also knew the DDS chip can do that. BTW, can we realized the function in FPGA. any comments, pls.
 

echo47

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You can implement the digital parts of a DDS in an FPGA, but not the analog parts such as the DAC, filter, and comparator.
 

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