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40nm vs 130nm cmos process and parasitic caps

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mirror_pole

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Hello guys,

Lets say i use the same dimensions for a transistor in both technologies, are the parasitic caps of smaller technologies still smaller? Im pretty unexperienced but would like to know if this is the case.

Im trying to "convert" a circuit from 40nm to 130nm facing some trouble with the dimensions. My goal is to get as close as possible to simulation results presented using 40nm process.
The biggest problem im facing is that to get somewhere decent bode plots i have to chose minimum device lenghts and im still not able to make wgbw equal to transition frequency.
 

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