// VerilogA for BGR_v2, decoder2, veriloga
`include "constants.vams"
`include "disciplines.vams"
module decoder2 (
binary_in , // 4 bit binary input
decoder_out, // 11-bit out
enable // enable for the decoder
);
input [3:0] binary_in;
input enable;
output [10:0] decoder_out;
electrical binary_in, decoder_out, enable;
//reg [10:0] decoder2_out;
always @(enable or binary_in)
begin
decoder_out=0;
if (enable) begin
case (binary_in)
4'h0: decoder_out=11'h0001;
4'h1: decoder_out=11'h0002;
4'h2: decoder_out=11'h0004;
4'h3: decoder_out=11'h0008;
4'h4: decoder_out=11'h0010;
4'h5: decoder_out=11'h0020;
4'h6: decoder_out=11'h0040;
4'h7: decoder_out=11'h0080;
4'h8: decoder_out=11'h0100;
4'h9: decoder_out=11'h0200;
4'hA: decoder_out=11'h0400;
default: decoder_out=11'h000;
endcase
end
end
endmodule