### Welcome to EDAboard.com

#### Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Status
Not open for further replies.

#### killersbeez

##### Newbie level 3 hello, i have question hot to program adder with 4 inputs in VHDL!

i have made this VHDL code is it correct?!
Library ieee;
Use ieee.std_logic_1164.all;

generic (dummy : time := 0 ns);
PORT( A,B,C,D : IN std_logic;
sum: OUT std_logic);
END ENTITY;

BEGIN
PROCESS(A,B,C,D)
BEGIN
if ( A = '0' and B = '0' and C = '0' and D = '0' ) then
sum<= '0'
else
if ( A = '0' and B = '0' and C = '0' and D = '1' ) then
sum<= '1'
else
if ( A = '0' and B = '0' and C = '1' and D = '0' ) then
sum<= '1'
else
if ( A = '0' and B = '0' and C = '1' and D = '1' ) then
sum<= '0'
else
if ( A = '0' and B = '1' and C = '0' and D = '0' ) then
sum<= '1'
else
if ( A = '0' and B = '1' and C = '0' and D = '1' ) then
sum<= '0'
else
if ( A = '0' and B = '1' and C = '1' and D = '0' ) then
sum<= '0'
else
if ( A = '0' and B = '1' and C = '1' and D = '1' ) then
sum<= '1'
else
if ( A = '1' and B = '0' and C = '0' and D = '0' ) then
sum<= '1'
else
if ( A = '1' and B = '0' and C = '0' and D = '1' ) then
sum<= '0'
else
if ( A = '1' and B = '0' and C = '1' and D = '0' ) then
sum<= '0'
else
if ( A = '1' and B = '0' and C = '1' and D = '1' ) then
sum<= '1'
else
if ( A = '1' and B = '1' and C = '0' and D = '0' ) then
sum<= '0'
else
if ( A = '1' and B = '1' and C = '0' and D = '1' ) then
sum<= '1'
else
if ( A = '1' and B = '1' and C = '1' and D = '0' ) then
sum<= '1'
else
if ( A = '1' and B = '1' and C = '1' and D = '1' ) then
sum<= '0'
else
sum <= 'X' ;
end if;
END PROCESS;
END functional;

Last edited:

#### Fl1pFl0p

##### Newbie level 4 • killersbeez

### killersbeez

points: 2

#### killersbeez

##### Newbie level 3 says this for me and i cant find what wrong there digi.vhdl:64: syntax error, unexpected t_PROCESS, expecting t_IF at PROCESS
v2cc: digi.vhdl: 1 errors

---------- Post added at 00:45 ---------- Previous post was at 00:27 ----------

find the problem! everything works, but is it a 4 input adder or its something other?!

#### Fl1pFl0p

##### Newbie level 4 This line shows the number of inputs:

IN STD_LOGIC_VECTOR(7 DOWNTO 0)

this is a 8bit adder. The ripple adder can be cascaded to as many bits as you would like. If you read the reference link above, and the for loop is causing confusion, try reading this example.

VHDL coding tips and tricks: 4 bit Ripple Carry Adder using basic logic gates

This is a gate level 4bit adder and test bench to simulate its behavior.

---------- Post added at 18:31 ---------- Previous post was at 18:15 ----------

O wooo ... did not see your code at the top. Where did that come from?

#### sanju_

##### Full Member level 3 hi
in your program their is no carry and instead of "if" you can use "case" would be better..
if you want to use "else if" better to use "elsif"....

you may be getting error in your code because you used so many "if" and one "end if"

Last edited:

#### vipinlal

##### Full Member level 6 One suggestion, VHDL offers elsif. So instead of using else if every time you can use elsif. The code will look cleaner and easy to debug.

You have used many "else if" in the above code, but doesnt have enough "end if" to cover them all.

Status
Not open for further replies.