anal0g
Newbie level 5
Hi,
This is a basic diff amp with a tail current of Iss, two NMOS input devices with load resistors Rd on both drains. The diff output is tapped off the drains of the two NMOS devices at the node that connects the drain to Rd.
The only thing that makes it a little different from a standard resistive load Differential amplifier is that both load resistors on the drains of the 2 NMOS devices (M1 and M2) connect to a third resistor R2 , and R2 then connects to the supply VDD. The load capacitance at the output is CL.
Without R2, i think the 3db bandwidth would be
1/(2pi(CL*Rd)) (assuming Rd<<ro)
What would it be with the addition of R2 in the circuit ?
Thanks
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This is a basic diff amp with a tail current of Iss, two NMOS input devices with load resistors Rd on both drains. The diff output is tapped off the drains of the two NMOS devices at the node that connects the drain to Rd.
The only thing that makes it a little different from a standard resistive load Differential amplifier is that both load resistors on the drains of the 2 NMOS devices (M1 and M2) connect to a third resistor R2 , and R2 then connects to the supply VDD. The load capacitance at the output is CL.
Without R2, i think the 3db bandwidth would be
1/(2pi(CL*Rd)) (assuming Rd<<ro)
What would it be with the addition of R2 in the circuit ?
Thanks
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