[SOLVED] 3-digit Frequency Counter

[Eshal]

Hello experts!

I have a lab project of 3-digit frequency counter. But we have given a circuit of 4-digit frequency counter circuit diagram. I am posting the given schematic here.

I have designed it in multisim. Here is my multisim snapshots.


I have built the circuit in multisim same as given in the schematic but it is not working. I am using 7-segment LED display common cathode. Its mean, I will have to connect CK pin to 5v. Right?

You can see multisim is running but nothing is displaying on the 7-segment LED.

Actually, I don't know what frequency should I given on the clock. I think, it should be 1Hz.
XFG1 is the clock signal
XFG2 is the signal of unknown frequency (signal, which frequency is to be determined)


Anybody help?

Regards,
Princess

 

[BradtheRad]

Since you have several stages of operation, it is a good idea to first confirm that each stage is doing its job.

Example, turn off the latch so you can see what is going on. Watch the output pins of the various IC's. Try to recognize the binary number from the four output pins, and to see the progression with each change.

Or, input various binary patterns at the decoder IC. See if you can get numerals on the led display.

Etc.

Actually, I don't know what frequency should I given on the clock. I think, it should be 1Hz.
XFG1 is the clock signal

Yes, you want the count to be done at a 1 Hz frequency.

There is a sequence of steps: (1) count, (2) unlatch, (3) display, (4) latch, (5) clear...
It must be done in exactly the right order (I hope I listed the above steps correctly). I do not know specifically how your counter IC does this. You must make sure, in order to get sensible results.

For my homebrew frequency counter I had to generate these timing pulses in sequence, using an external circuit, all within a few uSec of each other.

 

[xbased]

I am using 7-segment LED display common cathode. Its mean, I will have to connect CK pin to 5v. Right?

No. Common cathode must be connected to ground. Common anode conects to 5V.

**broken link removed**

 

[Eshal]

First of all, thank you all experts to help me.

@BradtheRad

Example, turn off the latch so you can see what is going on. Watch the output pins of the various IC's. Try to recognize the binary number from the four output pins, and to see the progression with each change.

Sir, can you help me how to perform and check operations of each IC? I try myself but it just few month before I started the digital electronics and suddenly we have been given with a project. So I don't know how to do it, neither I have knowledge about it much. But I can try. I have one week in order to complete it. Can you take me step by step?

Or, input various binary patterns at the decoder IC. See if you can get numerals on the led display.

Yes sir, I will then let you know.

Yes, you want the count to be done at a 1 Hz frequency.

How can you say this the count to be done at 1Hz frequency? What would happen if I give count of above 1Hz, 100Hz or 1KHz. Similarly, what would happen if I give the count less than 1Hz?

There is a sequence of steps: (1) count, (2) unlatch, (3) display, (4) latch, (5) clear...
It must be done in exactly the right order (I hope I listed the above steps correctly). I do not know specifically how your counter IC does this. You must make sure, in order to get sensible results.

I am sorry sir, I didn't get what do you want to say me in above quote.

Thank you.

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@xbased

No. Common cathode must be connected to ground. Common anode conects to 5V.

Ohh... I see.
Here is, I have done it correct now. But still not any display.

Its mean, my circuit has problem in it. Right?

Regards,
Princess

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What 74LS90 IC is using to count what? Means, how much it count and at what value it resets?
For example, if
R01=X
R02=X
R91=H
R92=H
then it gives output 1001 (9 in binary). But the circuit I have been given with from my teacher, here R02=CLK while other are open. What is the function of CLK at R02 and why are other open? What should be the expected output in this case?

 

[ALERTLINKS]

To start with,

I am using 7-segment LED display common cathode.

You need common anode display not common cathode.

See datasheet of 74LS47.
**broken link removed**
and its connection diagram.

And to test it,
https://www.edaboard.com/threads/37552/

 

[Eshal]

@ALTERLINKS
Hello sir, how are you?
Thank you for your reply sir.

How do you know I should use CA display not CK?

 

[ALERTLINKS]

https://elektroarea.blogspot.com/2010/03/74ls47decoder-bcd-4-bit-to-seven.html

 

[Eshal]

Can I use 74LS48 with CK? If so, then what should you say about limiting resistors?

 

[ALERTLINKS]

Always try to understand datasheet.
https://www.physics.rutgers.edu/ugrad/327/sn74ls48rev5.pdf


This is a stopwatch circuit. If you enable it for 1sec. You get the frequency.

 

[Eshal]

Ohhh.... I understand. 7448 is a decoder only, while 7447 is a decoder/driver. There is a difference between them. This is what we have not taught in the university.

 

[Eshal]

Yes sir, this is what I understand the difference between 7447 and 7448.

Now I have some other questions. We didn't use 74LS173 in the lab yet. But they have given it in the project. you can see. I don't know how it works and how 7490 works. why we are giving clock to R02?

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7448 is for CK
7447 is for CA

 

[ALERTLINKS]

The pulse on R02 resets counter to zero. It is to enable a window of time during which pulses on signal line are counted. If it is for 1sec, readout will be herts/sec (frequency). Then after reset another sample is taken.
**broken link removed**
**broken link removed**

 

[Eshal]

I didn't understand :|
If we want to reset the 7490 then why should we not connect R02 to High instead of clock?
The following configuration resets the 7490 output.
R01=H
R02=H
R91=L
R92=X
Where, X= any value either H or L

So why don't we use this instead clock?

 

[ALERTLINKS]

Let's look at the 7490 briefly to see how it works.
The 7490 is a decade counter, meaning it is able to count from 0 to 9 cyclically, and that is its natural mode. That is, QA, QB, QC and QD are 4 bits in a binary number, and these pins cycle through 0 to 9, like this:
QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

You can also set the chip up to count up to other maximum numbers and then return to zero. You "set it up" by changing the wiring of the R01, R02, R91 and R92 lines. If both R01 and R02 are 1 (5 volts) and either R91 or R92 are 0 (ground), then the chip will reset QA, QB, QC and QD to 0. If both R91 and R92 are 1 (5 volts), then the count on QA, QB, QC and QD goes to 1001 (5). So:
To create a divide-by-10 counter, you first connect pin 5 to +5 volts and pin 10 to ground to power the chip. Then you connect pin 12 to pin 1 and ground pins 2, 3, 6, and 7. You run the input clock signal (from the timebase or a previous counter) in on pin 14. The output appears on QA, QB, QC and QD. Use the output on pin 11 to connect to the next stage.
To create a divide-by-6 counter, you first connect pin 5 to +5 volts and pin 10 to ground to power the chip. Then you connect pin 12 to pin 1 and ground pins 6 and 7. Connect pin 2 to pin 9 and pin 3 to pin 8. Run the input clock signal (from the timebase or a previous counter) in on pin 14. The output appears on QA, QB and QC. Use pin 8 to connect to the next stage.

See in this proteus file how it is done.

 

[BradtheRad]

Sir, can you help me how to perform and check operations of each IC? I try myself but it just few month before I started the digital electronics and suddenly we have been given with a project. So I don't know how to do it, neither I have knowledge about it much. But I can try. I have one week in order to complete it. Can you take me step by step?

To simplify things, start by making a counter using just a 7490 and 7447, driving one digit.

Find out which pins need to be enabled or disabled (that is, high or low), so that it does what you want.

Add the other devices step by step.

How can you say this the count to be done at 1Hz frequency? What would happen if I give count of above 1Hz, 100Hz or 1KHz. Similarly, what would happen if I give the count less than 1Hz?

It is fine to reduce the time window so that it will divide by 10 or 100 or 1000, in case your incoming frequency is too high for your 3 digits to accommodate.

Likewise you can extend the time window to 10 seconds, so that the counter can handle an incoming frequency slower than 1 Hz.

 

[Eshal]

Hello friends.

Yesterday it was my first day with project. I tried today to check where is the mistake in my circuit. So I check it step by step. First, I check with my 74LS90 (decade or binary counter). I observed it is working fine and giving count from 0000 (0) upto 1001 (9). But problem is, it gets hold after two to three counts. Sometime it holds after five to six counts. See below,
0000
0001
0010
holds for 3 to 4 pulses of clock
0011
0100
0101
holds for 3 to 4 pulses of clock again
0111
1000
1001
0000
holds for 4 to 5 pulses of clock again
and so on.

means no continuous counting. Why does it gets hold?

Remember, it is just 74LS90. I just check 74LS90 yet and today was the second day of the lab project and tomorrow is the last day of the project lab for this week then next weak will be last for this.

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@ALTERLINKS
I have read it and understood how to take advantage of 74LS90 to any divide by number counter.
I have understood the working and purpose of decade counter.

@BradtheRad

It is fine to reduce the time window so that it will divide by 10 or 100 or 1000, in case your incoming frequency is too high for your 3 digits to accommodate.

Likewise you can extend the time window to 10 seconds, so that the counter can handle an incoming frequency slower than 1 Hz.

Sorry sir, didn't understand this.

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As a first step, what I have done today at university, I did the same at home with multisim.
I constructed this part (74LS90)
on multism
and it is working fine if I give R91 and R92 both are High regardless the R01 and R02.
Here is the the Reset/Count Truth Table. (attached)
the circled states are working fine


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Now, first three are fine and same outputs as shown in the Truth table. But when I want to get count on the output then LEDs are all low for last four states.
see here what I did on the multisim

Here is what I tried to do in order to get count, circled on the truth table,
If I give any of the last four states according to the Reset/Count Truth Table, the result is same i.e. no LED go high.

Since, last four states will give count on QA, QB, QC and QD. So I used clock where X is written in the Truth Table.


Why doesn't LEDs give count? They must count from 0000 (0) to 1001 (9). Right?

If this step is right then I will construct further circuit.
Please help me,

And kindly tell me how 74LS173 is working in my circuit. At our university they didn't teach us that IC which has 2 enable inputs.

Thank you experts.

 

[ALERTLINKS]

You see simulation in this this proteus design file with 74LS173. Did you simulated previous file i posted.

A video of action,

[video]http://tinypic.com/r/fmq3pc/6[/video]

 

[Eshal]

@ALTERLINKS

Hello sir, thank you for your help. Your gated counter is working well. But I want to know, why did you set your clock at CKA 6Hz? and why did you set your clock at R02 period of 4sec (f=250mHz), why? How do you come with the idea about CKA=6Hz and R02=250mHz?

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74LS173 is a Quad D-type flip flop with tristates. What is mean by tristate here? I mean, I know it has 3 output states but how?

How to check if IC is working properly or not? If I want to check it separately then what should I do?

And quad means here, 4 flip flops. Right?

 

[ALERTLINKS]

why did you set your clock at CKA 6Hz? and why did you set your clock at R02 period of 4sec (f=250mHz)

Just to observe visual simulator results easily( slow enough). If we set R02 clock at 0.5Hz(1sec on time, 1sec off time
we will see display 0-9 with input 0Hz-9Hz at CKA.)
Set CKA from 0-9Hz in this design and observe display


Tristate output:
In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines (such as a bus which cannot listen to more than one device at a time).

http://en.wikipedia.org/wiki/Three-state_logic

I know it has 3 output states but how?

When either M or N (or both) is (are) high, the output is disabled to the high-impedance state; however, sequential
operation of the flip-flops is not affected.


To compare and for further detail, have a look,
**broken link removed**
HCF4076B is similar.
http://www.datasheetcatalog.org/datasheet2/0/01diw8q66c4pz6f65ylel3xfwsky.pdf

 

[Eshal]

@ALTERLINKS.

Sir, the file 0-9Hz frequency counter.rar you have given, I constructed it already in same in the multisim in the noon. But still problem, no output is shown on the 7-segment. Everything is same as you described, I was confused about frequency too. But nothing is displaying on the 7-Segment.

You can see, everything is same. even frequencies and peak voltage, rise and fall times for both is 1us and simulator is running but nothing is being displayed. Sir, do you know what could be the problem? Is it multisim which has problem?

Thank you very much.

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I also want to know, it is the one stage which counts frequency from 0-9Hz. But my task is to construct the frequency counter which can count 000-999Hz. Means 3 digit is my task. Then what should be the clock frequency (R02) and signal frequency (CKA) given? For one digit, as ALTERLINKS did, I am using 500mHz at clock (R02) and 0-9 Hz at signal (CKA) which is working fine.