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2nd Order RC Filter Design

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ImperfectSeven

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I am working on making a 2nd order RC low pass filter to turn my PWM signal into a DC signal. I have set the system clock at 24 MHz and I have 10 bit resolution on my PWM so it has a frequency of about 23.4375 kHz. From what I have read it is recommended that the 3dB point should be about 1/5 of the PWM frequency. That puts my 3dB point around 4.5 kHz From what I understand I need to select my R and C values such that my f_n = 1/(2*pi*sqrt(R1R2C1C2)) is less than or equal to that 4.5 kHz, but I need my damping ratio to stay round 1. The problem I am having is that I don't know how to solve for the RC values without guessing and checking.

Here is what I have done:

3dB point = fn = 1/(2*pi*sqrt(R1R2C1C2))
damping ratio = d = (R1C1 + R1C2 + R2C2)/(2*sqrt(R1R2C1C2))

I pick some arbitrary value for f_n that is less than or equal to 4.5k
f_n = 1k = 1/(2*pi*sqrt(R1R2C1C2))
1/(2*sqrt(R1R2C1C2)) = 3.14k
(2*sqrt(R1R2C1C2)) = 318u *
(R1R2C1C2) = 25.33n (1)

equate my damping ratio to 1
(R1C1 + R1C2 + R2C2)/(2*sqrt(R1R2C1C2)) = 1
(R1C1 + R1C2 + R2C2) = (2*sqrt(R1R2C1C2)) *
(R1C1 + R1C2 + R2C2)= 318u (2)

At this point I get a little stuck and I wing it by pick an R1 and C1 value
R1 = 2k
C1 = 0.1u

After plugging those in to (1) and (2)
R2C2 = 126.65u
200u + 2kC2 + R2C2 = 318u
2kC2 = -8.65u
C2 = -4.325n

As you can see I get a negative capacitance value which obviously isn't possible.
I have tried adjusting what I set R1 and C1 to but once again I am in the guess and check realm.
Is there something I am missing about this filter?
 

From what I understand I need to select my R and C values such that my f_n = 1/(2*pi*sqrt(R1R2C1C2)) is less than or equal to that 4.5 kHz,
By selecting R and C values based on a certain formula you must have a particular circuit in mind.
You should know that there at least 20 different low pass topologies - which one did you select?
Without this information nobody can help you.
 
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    FvM

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Thank you for the quick response.
I am using a passive RC Low Pass filter I have attached an schematic.
Its a ladder network configuration of resistors and capacitors.
LP_Filter.JPG
 

Cut-off frequency, filter order and type would be selected based on perfornance criteria. For the present PWM DAC case, residual PWM ripple, bandwidth, settling time and overshoot are possible parameters of interest.

Residual ripple with your configuration will be considerably higher than 1 LSB, so we could guess, if either a higher order or lower cut-off frequency may be wanted.

Filter implementation in a particular topology would be the second step after defining the parameters. A lot of design tools can help you for it.
 
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    LvW

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I am looking to use the PWM as a DAC so the ripple and settling time are important factors that I have considered. I have concluded however that the ripple is much more important than the settling time as the signal does not need to change often and I would much rather have a steady output.
Residual ripple with your configuration will be considerably higher than 1 LSB, so we could guess
You are correct here, that is one problem I had in my first implementation of this filter. I had a 1mV/bit resolution but a 17mV ripple which caused an output voltage that would oscillate between +-1V around my desired level.
 

Thank you for the quick response.
I am using a passive RC Low Pass filter I have attached an schematic.
Its a ladder network configuration of resistors and capacitors.

Here is a calculator and analysis tool for 2nd order RC low pass filters that might help you: **broken link removed**. It supports many other filter types too.

J
 

Here is a calculator and analysis tool for 2nd order RC low pass filters that might help you: **broken link removed**. It supports many other filter types too.

J

Yes, I have actually come across that already, but I need to write a design and analysis report over my entire project and having a circuit that I guess and check the values of won't look to good.

I'm asking if there is a way for me to calculate the RC values given the conditions I would like to meet.
 

If I understand the definition of your damping ratio correctly, d = 1 refers to two decoupled cascaded first order low passes. That means, you can't achieve it in a purely passive second order filter, only approximate it by setting R2 >> R1, and R1C1 = R2C2.

Live would be much easier by adding a buffer amplifier, also allowing a true third order characteristic like Butterworth or Chebsyhev.
 
If I understand the definition of your damping ratio correctly, d = 1 refers to two decoupled cascaded first order low passes. That means, you can't achieve it in a purely passive second order filter, only approximate it by setting R2 >> R1, and R1C1 = R2C2.
That is correct, I know ideally I want 0.707 < d < 1, however with this configuration d cannot go below 1 so I aim to get it as close to 1 as possible.
I did not previously know that relationship and that does help explain why the values I selected work, but using the above equations I just ended up finding that R1C2 = 0 which means that one of them is 0.
I could make it a 3rd order, or add a buffer but from what I have read I don't really need them for this application and I am trying to do this with as little as possible.

What I have found is that if I use:
R1 = 2k
R2 = 1M
C1 = 0.1u
C2 = 200p
Then I get a 3dB frequency of about 800 Hz and a damping ratio of 1.001
Simulation shows that the settling time is about 1.5ms while the ripple is about 4mV
I think the ripple could cause some oscillation in my output voltage (I am using this PWM as a DAC to set a threshold for a high voltage boost converter circuit) <-- sorry about not mentioning that
but the oscillation would be almost 4 times less than what I saw before which would be about 1/4 V which is acceptable.
 

In practical terms, a resistance ratio of 1:10 or 1:20 should be sufficient, because the transfer characteristic doesn't change much by increasing it further. This should be considered if you don't want the output resistance rising too high.
 

Alright, so I changed my 1M to 40k and the 200p to 5n in my simulation, and you are right there is almost no change in the output, although this does put my 3dB point at 25 kHz which won't work for this application, it also increases my damping ratio from 1.001 to 1.025 which isn't enough to worry about. My main concern with that is the new 3dB point.
I guess what I'm getting from all of this is that there is no way to actually calculate the values for R and C, all I can do is create some conditions that must be met and then find some values that meet all of those conditions.
 

What I have found is that if I use:
R1 = 2k
R2 = 1M
C1 = 0.1u
C2 = 200p
Then I get a 3dB frequency of about 800 Hz......
With no load on the output, it should be -3dB at 510 Hz.

Alright, so I changed my 1M to 40k and the 200p to 5n in my simulation, and you are right there is almost no change in the output, although this does put my 3dB point at 25 kHz.....
With no load on the output, it should be -3dB at 494 Hz.
For accurate calculations you need to take the load impedance into account (and the source impedance, if it's significant).
 

With no load on the output, it should be -3dB at 510 Hz.
How did you come up with this value? The equations I have and the website listed above each come up with 795.77 Hz

For accurate calculations you need to take the load impedance into account (and the source impedance, if it's significant).
I don't think the source impedance is significant, but the load impedance I believe to be about 380k (it has a maximum capacitance of 18pF and a resistance of 320 ohms) at a frequency of 23.4375 kHz
 

How did you come up with this value?
I cheated and used a simulator, but it looks reasonable.

The equations I have and the website listed above each come up with 795.77 Hz
That's correct for a first order filter. With a second order filter, the response is about -6dB at that frequency because both filter sections reduce it by 3dB.

So the -3dB frequency for the 2'nd order filter is lower than that.
 

For a first order fc = 1/(2*pi*RC)
For a second order fc = 1/(2*pi*\[\sqrt{R1R2C1C2 }\]
If that is correct and I use the previous values then:
1st order:
fc1 = 1/(2*pi*2k*0.1u) = 795.77 Hz
fc2 = 1/(2*pi*1M*200p) = 795.77 Hz

2nd order:
fc = 1/(2*pi*\[\sqrt{2k * 1M * 0.1u * 200p }\] = 795.77 Hz

What am I doing wrong?
 

I have set the system clock at 24 MHz and I have 10 bit resolution on my PWM so it has a frequency of about 23.4375 kHz.
I have concluded however that the ripple is much more important than the settling time
Here's one way to do the calculations:

10 bits means 1024 steps, so if you want the ripple to be less than 1 LSB, you need about 60dB attenuation at 24KHz i.e. reduction by a factor of about 1000.

If you're using a second order RC filter, that means that each section should give about 30dB attenuation at 24KHz i.e. reduction by a factor of about 30. So Fo for each RC stage should be about 24KHz / 30 = 800Hz.

The values you've got agree nicely with that. I'd probably just change the 2'nd RC so the output impedance isn't so high. Maybe something like:
R1 = 2k2
R2 = 22K
C1 = 0.1uF
C2 = 10nF

- - - Updated - - -

What am I doing wrong?
That formula isn't really useful. It just gives the mean of the Fc for each section. It also doesn't take into account the interaction between them.

P.S. Something went wrong with your LaTeX. :-?
 

P.S. Something went wrong with your LaTeX.
Ha, I'd say so. Guess I should have previewed that one.

reduction by a factor of about 1000.
by this you mean that I am reducing my PWM signal by a factor of 1000 correct?
If so that means my ripple will be VPWM * duty cycle / 1000 and thus a maximum of 3.3mV at 100% (PWM output is 3.3V)

Now that I have realized that I actually need 2268 counts so that each count is about 1.46mV which means my ripple needs to be much smaller than that.
So now I need about 73dB (reduction of 4467) at 10.577 kHz and thus about 37dB (reduction of about 67) at each stage
So for each stage fc should be at 10.577 kHz / 67 = 167.23 ≈ 158 Hz

Is that correct?

I then get the following:
R1 = 11k
R2 = 110k
C1 = 0.1u
C2 = 10n

would those values be acceptable or is the output impedance too high?
 
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So for each stage fc should be at 10.577 kHz / 67 = 167.23 ? 158 Hz

Is that correct?
Yes, but I don't know where you got 2268 from.

Maybe it's worth using a higher order filter?
For 2'nd order, Fc ? 165 Hz
For 3'rd order, Fc ? 650Hz
For 4'th order, Fc ? 1300 Hz

The pictures below compare the frequency response of the 2'nd, 3'rd and 4'th order filters. 3'rd order looks like a worthwhile improvement to me, but I don't know your requirements.



I then get the following:
R1 = 11k
R2 = 110k
C1 = 0.1u
C2 = 10n

would those values be acceptable or is the output impedance too high?
I don't know. It depends what the input and output will be connected to.
For a 3'rd order filter, you'd have a smaller input impedance and/or a bigger output impedance, so that's also a factor. Another option is to have less than 10 to 1 ratio between the values.
 
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I see that the points addressed in post #4 finally come into play. But I'm yet missing a criterion to decide about a possible range of filter cut-off frequencies, that's the bandwidth respectively settling time required by the application.
 

the bandwidth respectively settling time required by the application.
I'm not quite sure what you mean by this. The settling time of the filter is not too important, I have actually been letting it slip to around 500 ms.

Yes, but I don't know where you got 2268 from.
I get the 2268 because I found out that 1V on my high voltage side corresponds to 1.46mV out of my PWM.
Thus, if I would like my system to increase 1 V at a time on the HV side I need my PWM to increase by about 1.46mV.
If the maximum voltage for the PWM is 3.3V then 3.3/1.46m = 2267.3.

I don't know. It depends what the input and output will be connected to.
Both input and output are connected to the microcontroller that I am using for this application
The input impedance of the microcontroller is about 460k
 

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